This invention relates generally to ferroelectric capacitors and corresponding ferroelectric memories and, more particularly, to an improved test and fabrication method for integrated circuit ferroelectric memories.
It is well known that certain materials such as lead zirconate titanate ("PZT"), barium titanate, phase III potassium nitrate, and others are "ferroelectric" in that they can retain a reversible electric polarization in the absence of an applied electric field. The stable polarization results from the alignment of internal dipoles with the perovskite crystal units in the ferroelectric material. Application of an electric field exceeding a critical level known as the "coercive voltage" causes the alignment of the dipoles. Application of the electric field across a ferroelectric material causes the alignment of the dipoles in one direction. Reversal of the polarity of the applied field also reverses the alignment of the internal dipoles. However, it may be noted that the coercive voltage may not always be well defined in some ferroelectric materials. Also, it is known that the rate of alignment of the dipoles is related to the overdrive voltage, i.e. the amount by which the applied voltage exceeds the coercive voltage. The position of the dipoles and the associated electric charge in response to an applied electric field can be detected with appropriate sensing circuitry. Ferroelectric materials such as PZT, therefore, can be used as the dielectric material in a ferroelectric capacitor that in turn is used as the memory element in a nonvolatile memory cell. In order to be useful as the memory element in a semiconductor nonvolatile memory, however, a ferroelectric capacitor must retain data for an extended period of time at a given storage temperature. The ability to retain data, also known as retention performance, is adversely affected by a multi-faceted mechanism known generally as imprint. The term imprint is used because it implies that the history of the data stored in the ferroelectric capacitor affects its retention performance. Specifically, storage of data of the same binary value for a long period of time at temperature degrades the ability of the ferroelectric capacitor to retain data of the opposite binary value.
Data storage and imprint degradation of retention can be explained by examining changes in a hysteresis loop associated with a ferroelectric capacitor. Referring now to FIG. 1A, a normal hysteresis loop 10 for a ferroelectric material is shown as a plot of the polarization or charge on the y-axis corresponding to the applied electric field or voltage on the x-axis. Two different stable polarization states 12 and 14 are illustrated that exist at a zero applied electric field. Binary data is stored in the ferroelectric capacitor by setting the polarization in either of the two states 12 or 14. These stable states of polarization can be designated "up" or "down" to imply a polarity or direction to the polarization. The initial or virgin state of a capacitor prior to the application of any electric field is not described by the single hysteresis loop 10 since no net polarization has been set into the capacitor. The virgin state exists at the origin of the plot, i.e. zero applied field and zero polarization. Note that a normal hysteresis loop 10 is generally centered around the origin of the plot. Application of an electric field of a sufficient magnitude polarizes, or "poles", the ferroelectric capacitor and sets it into one of the up or down polarization states 12 or 14. It should be noted that a ferroelectric dielectric material such as PZT is ferroelectric only below a characteristic temperature known as the Curie temperature. For PZT this temperature is about 400.degree. Centigrade. Above the Curie temperature the hysteresis loop 10 is collapsed and the dielectric material is paraelectric, i.e. the material loses its ability to retain an electric polarization in the absence of an applied electric field.
A ferroelectric memory cell 11 built with ferroelectric capacitors C1 and C2 is shown in FIG. 1B. Each of capacitors C1 and C2 ideally have a normal hysteresis loop 10 as shown in FIG. 1A. Ferroelectric memory cell 11 is a two transistor, two capacitor ("2T-2C") memory cell that includes pass transistors M1 and M2 each serially coupled to ferroelectric capacitors C1 and C2. The data states of memory cell 11 are defined by complementary polarization states in the ferroelectric capacitors. For example, an up polarization state in capacitor C1 and a down polarization state in capacitor C2 may represent a logic "one", while a down polarization state in capacitor C1 and an up polarization state in capacitor C2 may represent a logic "zero." As in a typical DRAM cell, memory cell 11 includes a word line 13 coupled to the gates of transistors M1 and M2, and, since the cell is complementary, complementary bit lines 17 and 19, respectively coupled to the drains of transistors M1 and M2. In addition to the familiar word and bit lines, ferroelectric memory cell 11 also includes an active plate line coupled to the bottom plate of capacitors C1 and C2 that is pulsed during both reading and writing operations.
Flipping the polarization between the two stable states of a ferroelectric material, or "switching", evolves a significant amount of charge that can be detected by an electrical sensing circuit. Significantly more charge is evolved by switching than if no change in the polarization state occurred. Consequently, the stored state, or data value, is detected by electrically pulsing the ferroelectric capacitor and measuring the amount of charge evolved. This state-dependent difference in evolved charge with the application of a voltage pulse is illustrated in FIGS. 2A and 2B. In FIG. 2A a first amount of charge, Q.sub.1, is evolved by switching the ferroelectric capacitor from stable state 14 to a saturated point 16 on hysteresis loop 10. Charge Q.sub.1 is referred to as the "switched charge" and always corresponds to a flipped polarization state. In HG. 2B a second amount of charge, Q.sub.2, which is significantly less than charge Q.sub.1, is evolved by driving the ferroelectric capacitor from stable state 12 to a saturated point 16 on hysteresis loop 10. Charge Q.sub.2 corresponds to sensing the same polarization state. The difference in charges Q.sub.1 and Q.sub.2 can be detected by the electrical sensing circuitry in a non-volatile memory.
Imprinting degrades the hysteresis loop 10 and the opposite state data retention performance by shifting the loop along the x-axis and by distorting the shape of the loop, which are both illustrated in FIGS. 3A-3C, as well as by other mechanisms. Both the direction of the loop shift and the shape of the loop distortion can reduce the charge available for sensing opposite state data. Referring now to FIG. 3A, a normal hysteresis loop 10 is shown, wherein a full Q.sub.1 charge is produced when the data state is flipped from initial state 14. A distorted hysteresis loop 10A is shown in FIG. 3B, wherein a charge Q.sub.1A less than charge Q.sub.1 is produced when the data stated is flipped from initial state 14A. A shifted hysteresis loop 10B is shown in FIG. 3C, wherein a charge Q.sub.1B less than charge Q.sub.1 is produced when the data stated is flipped from initial state 14B. The shift and distortion mechanisms are also known by other names. Shift of the hysteresis loop 10 on the x-axis is also known as "compensation", which produces an asymmetric loop, and loop distortion is known as "relaxation".
The loss of charge that is needed to electrically sense the opposite data state (Q.sub.1 -Q.sub.2, as shown individually in FIGS. 2A and 2B) is made more apparent by baking a poled ferroelectric capacitor for long time periods at elevated temperatures above room temperature but below the Curie temperature. Referring now to FIG. 4, the charge available for detection by an electrical sensing circuit decreases linearly with the logarithm of time, and the slope of this decrease depends on temperature. This time and temperature dependence of the opposite state charge is called "aging" due to its functional time dependence. Line 18 represents the decrease in charge with time at a first temperature T.sub.1. Line 20 represents the greater decrease in charge with time at a second elevated temperature T.sub.2. The charge value for either line 18 or 20 is eventually reduced to a critical or cutoff value at which insufficient charge exists for electrically distinguishing the state of the data. Retention failure occurs when the available charge is degraded to the cutoff charge.
Unfortunately, conventional integrated circuit fabrication and test methods involve significant thermal treatment after the ferroelectric capacitors have been poled, causing further degradation of opposite state retention performance prior to shipment to the customer. These thermal treatments are encountered as bakes for screening retention performance prior to packaging. Thermal treatments are used in screening to elevate the testing temperature, which in turn desirably decreases testing time. Thermal treatments are also typically used in molding and curing steps in a plastic packaging process.
Blind Build Process Flow
One ferroelectric memory integrated circuit process flow that avoids aging induced charge degradation during manufacturing is to "blind build" or avoid poling the capacitors until after packaging. The ferroelectric capacitors in the memory array thus remain in the virgin state and no distortion or shifting occurs to the hysteresis loop. Since the memory parts are not tested, no electric field has been applied across the ferroelectric capacitor and no net polarization exists. With no net polarization there is no driving force for the imprint mechanism and capacitor degradation is greatly reduced during the subsequent thermal treatments of the packaging process. The test and packaging process steps for the blind build process flow are shown in FIG. 5. Process flow 22 includes wafer fabrication step 24; packaging step 26, which may include heat treatments below the Curie temperature; and electrical testing step 28.
The blind build process flow is somewhat unsatisfactory for several reasons. Package costs are raised because bad die are not screened out at wafer level test and undergo the unnecessary expense of packaging. Quality is also negatively impacted since no rapid feedback is provided to wafer manufacturing for process control. Efforts to improve the yield of finished good parts are difficult since yield loss at the packaging step cannot be distinguished from yield loss during wafer fabrication.
What is desired, therefore, is a method for improving a conventional ferroelectric memory wafer test and plastic package flow so that imprint degradation of switched charge can be minimized or eliminated.